1. Technical Field
The present invention relates to a level shift circuit that transmits a signal of a system on the primary side of an input to a system on the secondary side that is operated at an operating voltage different from an operating voltage of the system on the primary side of the input.
2. Background Art
In a circuit such as a half bridge driving circuit to which a power supply voltage of a high voltage system power supply is applied, a level shift circuit is used for driving a switching device on the high voltage side by a signal in a low voltage system.
In Japanese Patent No. 3,429,937, an example of a half bridge driving circuit is shown which uses a level shift circuit. In the following, an explanation will be made with respect to such a related level shift circuit with reference to FIG. 5, a circuit diagram showing a half bridge driving circuit using the related level shift circuit.
In FIG. 5, an output circuit 1 is provided with switching devices XD1 and XD2 connected in series to form a half bridge across which an output voltage E of a high voltage power supply PS is applied. For the switching device XD1 on the high side, a device such as an N-channel or P-channel MOS transistor or an N-type or P-type IGBT (Insulated Gate Bipolar Transistor), for example, is used. For the switching device XD2 on the low side, a device such as an N-channel MOS transistor or an N-type IGBT, for example, is used. Here, for the switching devices XD1 and XD2, N-channel MOS transistors or N-type IGBTs are to be used. To the switching devices XD1 and XD2, diodes DH and DL (parasitic diodes or commutating diodes) are connected, respectively, in inverse parallel.
A high side driving unit 2 is provided with the above described level shift circuit, a high side driver 21 that receives the output of the level shift circuit to carry out on-off control of the switching device XD1 and a power supply PS1.
The level shift circuit is a section of the high side driving unit 2 except the high side driver 21 and the power supply PS1. Namely, the level shift circuit is formed of a first series circuit including a resistor LSR1 and an N-channel MOS transistor HVN1, a second series circuit including a resistor LSR2 and an N-channel MOS transistor HVN2, a latch malfunction protecting circuit 22, a latch circuit 23 and diodes D1 and D2. The latch malfunction protecting circuit 22 has one input terminal connected to a series connection point (a first connection point) P1 in the first series circuit and has the other input terminal connected to a series connection point (a second connection point) P2 in the second series circuit.
The level shift circuit makes an output signal SH of the latch circuit 23 inputted to the high side driver 21 as a level-shifted signal.
The output terminal of the high side driver 21 is connected to the gate terminal of the switching device XD1 on the high side. Moreover, the negative side (low voltage side) power supply terminal of each of the latch malfunction protecting circuit 22, the latch circuit 23, the high side driver 21 and the power supply PS1 is connected to a third connection point P3 as a series connection point of the switching devices XD1 and XD2. To the latch malfunction protecting circuit 22, the latch circuit 23 and the high side driver 21, an output voltage E1 of the power supply PS1 is applied.
Each of the first series circuit including the resistor LSR1 and the N-channel MOS transistor HVN1 and the second series circuit including the resistor LSR2 and the N-channel MOS transistor HVN2 is connected between a power supply line L1 (the voltage thereof is to be denoted as Vb), connected to a positive side (high voltage side) terminal of the power supply PS1, and a ground (GND) line L2.
To the gates of the N-channel MOS transistors HVN1 and HVN2, a set signal (set) and a reset signal (reset) as input signals to the level shift circuit are inputted, respectively. The set signal (set) and the reset signal (reset) are signals in the low voltage system.
The set signal (set) is a signal instructing a timing of initiation of the on-period (termination of the off-period) of the switching device XD1 on the high side. The reset signal (reset) is a signal instructing a timing of initiation of the off-period (termination of the on-period) of the switching device XD1.
The diodes D1 and D2 have their anodes commonly connected to the third connection point P3 and have their cathodes connected to the first connection point P1 and the second connection point P2, respectively. The diodes D1 and D2 are provided for the purpose of clamping level shift drain signals (setdrn and resdrn) outputted from the first connection point P1 and the second connection point P2, respectively, so that no voltages of the level shift drain signals become not less than a voltage Vs at the third connection point P3, that is, for the purpose of preventing an overvoltage from being inputted to the latch malfunction protecting circuit 22.
A low side driving unit 3 is provided with a low side driver 31 carrying out on-off control of the switching device XD2 on the low side and a power supply PS2 applying a power supply voltage E2 to the low side driver 31. The low side driver 31 amplifies an input signal to input the amplified signal to the gate terminal of the switching device XD2. The switching device XD2 is turned-on (conducted) when the level of an input signal to the low side driver 31 is an “H (High)” level and is turned-off when the level of an input signal is an “L (Low)” level.
FIG. 6 is a timing chart for explaining a latch operation by a set and reset signals in the level shift circuit. In the timing chart, a set signal (set) with the level thereof becoming the “H” level makes the N-channel MOS transistor HVN1 turned-on to output a level shift drain signal (setdrn) with an “L” level from the first connection point P1. While, a reset signal (reset) with the level thereof becoming the “H” level makes the N-channel MOS transistor HVN2 turned-on to output a level shift drain signal (resdrn) with an “L” level from the second connection point P2.
Here, as is shown by a chain line in FIG. 5, consider a state in which the latch malfunction protecting circuit 22 is ignored to allow the level shift drain signals (setdrn and resdrn) to be directly inputted from the first and second connection points P1 and P2, respectively, to the latch circuit 23. In this case, in a period from the time at which the level of the level shift drain signal (setdrn) changes from an “H” level to an “L” level to the time at which the level of the level shift drain signal (resdrn) changes from an “H” level to an “L” level, the latch circuit 23 latches (holds) an “H” level to provide the output signal SH as an “H” level signal to the high side driver 21. Therefore, in the latch period, by an “H” level signal “HO” outputted from the high side driver 21, the switching device XD1 is to be turned-on.
The turning-on and -off of the switching devices XD1 and XD2 are carried out mutually complementarily (when the one is made turned-on, the other is made turned-off) except for a dead time in which both of them are made turned-off together. Then, a voltage Vs at the third connection point P3 becomes approximately the ground voltage when the switching device XD2 is turned-on and becomes the voltage approximately equal to the output voltage E of the high voltage power supply PS when the switching device XD1 is turned-on.
A load RL is connected between the third connection point P3 and the ground line L2 to be driven by the electric power outputted from the third connection point P3.
Here, consider the instant when a state in which the switching device XD2 is turned-on is switched into a state in which the switching device XD1 is turned-on. With the switching between both of the states, the voltage Vs at the third connection point P3 is promptly increases from the ground voltage to the output voltage E of the high voltage power supply PS as shown in FIG. 7, a timing chart for explaining dv/dt noises. At this time, both of the N-channel MOS transistors HVN1 and HVN2 made turned-off together cause erroneous signals known as dv/dt noises that will be explained later to be superposed on signals at the first and second connection points P1 and P2, respectively, which results in “L” levels in the levels of the first and second connection points P1 and P2 together. When the voltage levels of the first and second connection points P1 and P2, respectively, become “L” levels together, a malfunction is to be induced that causes the operation of the latch circuit 23 (formed by a set-reset flip-flop, for example) to be indeterminate, that is, a malfunction that causes the switching device XD1 to be indeterminate as to whether the switching device XD1 is turned-on or turned-off. In FIG. 7, the level shift drain signals (setdrn and resdrn) before the increase in the voltage Vs are regular signals being the same as those shown in FIG. 6. In the following, an explanation will be made with respect to dv/dt noises.
The voltage Vb of the power supply line L1 becomes a voltage which is a sum of the voltage Vs and the output voltage E1 as a constant voltage. Therefore, the rising of the voltage Vs is to cause the similar rising of the voltage Vb (both voltages have equal differential coefficients). Namely, the voltage Vb applied to the first series circuit including the resistor LSR1 and the N-channel MOS transistor HVN1 and the second series circuit including the resistor LSR2 and the N-channel MOS transistor HVN2 is to increase.
Because of the presence of parasitic capacitances Cds1 and Cds2 between the source and drain of the N-channel MOS transistor HVN1 and between the source and drain of the N-channel MOS transistor HVN2, respectively, when the variation in the voltage Vb is prompt, the voltage changes at the first and second connection points P1 and P2, respectively, can not follow the variation. This increases the potential difference between the voltage Vb and each of the first and second connection points P1 and P2. This, when viewed from the latch circuit 23, is to cause the voltage at each of the terminals of the latch circuit 23 to decrease simultaneously. The above described dv/dt noises are thus produced.
The latch malfunction protecting circuit 22 is provided for the purpose of avoiding the influences of the dv/dt noises. In the following, an example of the configuration of the latch malfunction protecting circuit 22 and its operation will be explained with reference to FIG. 8, a circuit diagram showing an example of a configuration of a related latch malfunction protecting circuit.
In the latch malfunction protecting circuit 22, one of input terminals to which a level shift drain signal (setdrn) is inputted is connected to one of input terminals of a NOR circuit G1 and, along with this, is connected to one of input terminals of a NAND circuit G3 through an inverter circuit G2. Moreover, the other input terminal to which a level shift drain signal (resdrn) is inputted is connected to the other input terminal of the NOR circuit G1 and, along with this, is connected to one of input terminals of a NAND circuit G5 through an inverter circuit G4. In addition, the output terminal of the NOR circuit G1 is connected to the other input terminal of the NAND circuit G3 and the other input terminal of the NAND circuit G5 through an inverter circuit G6.
The latch malfunction protecting circuit 22 having such a configuration is operated as follows. Namely, when the dv/dt noises shown in FIG. 7 are produced at the first and second connection points P1 and P2, the dv/dt noises are respectively inputted to both of the input terminals of the latch malfunction protecting circuit 22. At this time, from the inverter circuits G2 and G4, “H” level signals are respectively outputted and, from the NOR circuit G1, an “H” level signal is outputted. As a result, an “L” level signal is outputted from the inverter circuit G6. Thus, from each of the NAND circuits G3 and G5, an “H” level signal is to be outputted as an output signal of the latch malfunction protecting circuit 22.
The latch circuit 23 connected to the latch malfunction protecting circuit 22 is formed with a circuit such as a reset-set flip-flop operated with input signals in negative logic (a set or reset operation is carried out with an input in an “L” level). Therefore, the latch circuit 23 carries out no latch operation when a signal in an “H” level is inputted to a set terminal or a reset terminal. Namely, the latch circuit 23 keeps the state before dv/dt noises are produced to cause the signal in the “H” level to be inputted thereto, by which the switching devices XD1 is also made to keep the previous state. In this way, the latch malfunction protecting circuit 22 functions so as to prevent the latch circuit 23 from being brought into an indeterminate state (see FIG. 7) when dv/dt noises are produced, that is, so as to protect the latch circuit 23 against malfunction.
[Patent Document 1] Japanese Patent No. 3,429,937
In the level shift circuit, when the level of the set signal (set-1) becomes an “H” level as shown in FIG. 9, a timing chart for explaining operations of the related level shift circuit shown in FIG. 5, the N-channel MOS transistor HVN1 is turned-on, by which the level of a level shift drain signal (setdrn-1) changes to an “L” level. In this case, there is no change in the level of the reset signal to operate no latch malfunction protecting function of the latch malfunction protecting circuit 22. Thus, the latch circuit 23 carries out a normal latch operation. As a result, an output signal HO-1 of the high side driver 21 rises with a delay by a delay time to characteristic to the circuits 22 and 23 and the high side driver 21 to turn-on the switching device XD1. The turning-on of the switching devices XD1 causes a level shift drain signal (resdrn) with an “L” level to be outputted from the second connection point P2 by the above described dv/dt noise produced with the rising of the voltage Vs. The signal (resdrn), however, is blocked by the latch malfunction protecting circuit 22. Therefore, the latch circuit 23 keeps the latch operation thereof.
Incidentally, the voltage Vs normally increases when the switching device XD1 is switched from a turned-off state to a turned-on state (at this time the switching device XD2 is switched from a turned-off state to a turned-on state). In addition to this, however, the voltage Vs sometimes increases also in a dead time (set for preventing a feedthrough current from flowing) in which both of the switching devices XD1 and XD2 are made turned-off.
Namely, the turning-off of the switching device XD2 when the switching device XD2 is in a state of being turned-on to cause a current to be flowing from the load RL (to be an inductive load that makes prompt cut off of a current hard) to the output circuit 1 as a component of the converter (when the switching device XD2 is in a state of becoming a current sink device) causes a current, flowing in from the load RL in the dead time, to have nowhere to flow in. Thus, stray capacitance of the line at the voltage Vs (the line connected to the third connection point P3) is charged by the current to promptly increase the voltage Vs.
Moreover, an increase in the voltage Vs up to the voltage of making the diodes DH connected in parallel to the switching device XD1 (the output voltage E of the high voltage power supply PS +the forward voltage of the diode DH) makes the diode DH turned-on so as to allow a current to come to flow from the load RL to the high voltage power supply PS through the diodes DH.
Here, an explanation will be made with respect to the case in which the level of a set signal (set-2) becomes “H” level when the voltage Vs is rising due to the presence of a dead time, that is, the case in which the rising period of the voltage Vs and the time at which the level of the set signal (set-2) becomes “H” level are simultaneous.
In this case, with each of the levels of the level shift drain signals (setdrn-2 and resdrn) being brought to “L” level by dv/dt noises produced with the rising of the voltage Vs, that is, with the latch malfunction protecting circuit 22 carrying out a protecting operation, the level of the set signal (set-2) becomes “H” level. Therefore, until the protecting operation period of the latch malfunction protecting circuit 22 is terminated (until the period during which dv/dt noises are produced is terminated), the set signal (set-2) is not transmitted to the latch circuit 23 to thereby cause an output signal HO-2 of the high side driver 21 to be to rise after a long blank period (tb (>ta)).
Furthermore, in the case when the level of the set signal (set-3) becomes “H” level after the rising of the voltage Vs due to the presence of a dead time has terminated, the level of the set signal (set-3) becomes “H” level with no malfunction protecting function of the latch malfunction protecting circuit 22 being operated. Thus, an output signal HO-3 of the high side driver 21 rises with a delay by the delay time to characteristic to the circuits 22 and 23 and the high side driver 21 and, at the same time, the switching device XD1 is made turned-on.
In the case in which the voltage Vs rises in a period such as a dead time period as is described above, the turning-on operation of the switching device XD1 is largely delayed due to the above blank period tb, so that a power loss by the diodes DH connected in parallel to the switching devices XD1 becomes a problem. Thus, a technique is desired which permits the fastest possible turning-on of the switching device XD1.
Accordingly, an object of the invention is to provide a level shift circuit which can reduce the delay in the turning-on operation caused by a circuit that takes countermeasures against dv/dt noises produced by a high side switching device forming a circuit such as a half bridge.